This invention relates in general to frequency dividing circuits, and more particularly, to a fractional frequency divider for providing an output clock signal operating at a frequency equal to that of the input clock signal divided by the ratio of two integer values.
The need to generate a lower frequency clock signal from a higher frequency timing base signal is common in many of the electronic arts. In the field of data communications, for example, common operating frequencies for transmitting data over a modem link are 1200, 2400 and 9600 baud which may be realized by dividing a 1.152 MHz input clock signal by 960, 480 and 120, respectively. The conventional technique for generating the lower frequency output clock signal typically involves decrementing a counter preset to an integer value N once for each period of the input clock signal, hereinafter referred to as linear frequency division. The output clock signal remains logic zero until the counter reaches zero at which time the linear frequency divider generates one pulse and reloads the counter with the integer N. Thus, the linear frequency divider produces one output period every N input periods, i.e., the input clock is divided by N. The 1.152 MHz input clock signal is typically developed via a dedicated crystal oscillator designed specifically for such data communication purposes. It would be desirable to eliminate the 1.152 MHz crystal oscillator thereby simplifying the system design and reducing the manufacturing costs. This could be accomplished by using another high frequency clock signal, say a 10 MHz microprocessor clock already available in the system; however, in order to develop the appropriate operating frequencies, i.e., 1200, 2400 and 9600 Hz, the 10 MHz clock signal must be divided by the non-integer values 8333.33, 4166.67 and 1041.67, respectively. In practice, the high frequency timing base clock signal is typically divided in multiple steps of smaller increments per step to achieve the aforementioned operational frequencies.
Consequently, fractional frequency dividers have been developed to divide the frequency of the input clock signal by a non-integer value such as the ratio N/D where N and D are integers and N is greater than D. One such fractional frequency divider is the well known phase lock loop which can produce a virtually jitter free output clock signal having a predetermined frequency and duty cycle. However, many applications in data communications require synchronization between the edges of the input clock signal and the lower frequency output clock signal; a feature not available with phase locked loops. Furthermore, the phase lock loop is relatively complex and expensive to implement requiring substantial logic circuitry and a reference clock signal operating at a much higher frequency than even the input clock signal being divided. Hence, the phase lock loop is not a viable solution for many data communication applications because of the synchronization problems and excessive complexity.
Another fractional frequency divider may be achieved with the linear frequency divider wherein, for the example of a 7/2 (N=7, D=2) divider ratio, the frequency divider must generate two output pulses for every seven pulses of the input clock signal. For such an implementation, the output clock signal may remain logic zero for five decrements of the counter followed by alternating logic one and logic zero at the rate of the input clock signal during the next two consecutive cycles of the input clock signal thereby producing one longer period (six cycles of the input clock signal) and one shorter period (one cycle of the input clock signal) over the seven cycles of the input clock signal. The repeating output clock signal comprising alternating long and short periods is noticeably non-symmetrical and can be even more so with other divider ratios N/D, such as N=13 and D=5. Since the output clock signal is often applied as the input clock signal to another frequency divider circuit further downstream for providing the multiple division steps to reach the desired low frequency operational clock signal, the non-symmetry of the output clock signal can be a major problem in form of undesirable jitter in the operational clock signal.
Hence, what is needed is a frequency divider circuit for providing an output clock signal operating at a fractional frequency of the input clock signal while maintaining a substantially symmetrical output waveform thereby reducing the jitter for lower frequency operational clock signals generated therefrom.